----------------------------------------------------------------------
-- Delay of Nx16 registers (shift register)
-- Stephen West, James Carroll
-- BYU ECEn 620, October 2008
----------------------------------------------------------------------
Library ieee;
	use ieee.std_logic_1164.all;
	use ieee.numeric_std.all;
	
entity Delay16 is
	generic(
		delay16:integer:=1;
		word_length:integer:=8;
		code_vector_length:integer:=16;
		system_word_length:integer:=12
	);
	port(
		clk: in std_logic;
		input :in std_logic_vector(code_vector_length-1 downto 0);
		output: out std_logic_vector(code_vector_length-1 downto 0)
	);
end entity;

architecture Delay16 of Delay16 is
	component Delay is
    	generic(
    		delay:integer:=1
    	);
    	port(
    		clk, input :in std_logic;
    		output: out std_logic
    	);
    end component;
begin
	delay16x:for N in 0 to code_vector_length-1 generate
		delay_1:Delay
			generic map(delay=>delay16)
			port map(clk=>clk, input=>input(N), output=>output(N));
	end generate;
end architecture;